The invention relates to computer generated displays and in particular to an improved display memory controller.
Within the architecture of many personal computers, graphics and video data are stored in a display memory. The interface to this display memory is through a memory controller often contained within a graphics/video controller subsystem.
Typically, there are at least four devices in the computer system that can access the display memory. These devices are the CRT controller, real time video controller, bitBLT engine, and system logic (CPU) interface. The CRT controller reads data out of display memory and supplies it to a monitor interface to be displayed on the monitor such as a CRT or LCD display. The real time video controller collects streaming video data from an external video source and writes it to display memory. The bit block transfer (bitBLT) engine controls the movement of rectangular blocks of data from one area of display memory to another. The system logic (CPU) interface passes along display memory read and write requests from the host CPU.
A computer graphics monitor is, by nature, a two-dimensional pixel-oriented device, whereas the display memory is, by nature, a linear, byte-oriented device. In a linear memory, the byte(s) of data which defines the nature of the display that is to be generated at a particular pixel location is located at a specific location within the memory and is located by a single address rather than by two or more coordinates. When the display memory is to be accessed, the x and y coordinates of the pixel that needs to be read or written must be provided. Within the memory controller a translation must occur from the x,y pixel coordinate to the linear display memory address where the data for the pixel is stored. This display memory address may be expressed in the form of an "offset", that is the distance between the actual address of the data for the pixel and the initial address in the display memory at which the display data begins. Currently, within common personal computer architectures, the display memory address of a pixel at coordinate x & y is calculated by multiplying the number of pixels per line of the display raster (pitch) by the "y" coordinate of the pixel location, then adding the "x" value of the pixel location. Within the memory itself, the data for the pixels are stored in raster order starting with the data for the pixel at the top left corner and ending with the data for the pixel in the bottom right corner. The actual address offset in display memory will depend upon the color depth that is being used to store the graphics data (e.g. 4 bits-per-pixel (bpp), 8 bpp, 16 bpp, 24 bpp, 32 bpp, etc.) By way of example, in a computer display with 640 pixels in the "x" direction and 480 pixels in the "y" direction (e.g. 640.times.480 screen resolution), consider a pixel at coordinate x=240, y=160. The address (offset) of the data for this pixel would be (160.times.640)+240=102,640 (decimal).
The translation in the memory controller from the x,y pixel address to the corresponding offset in display memory requires a "multiplier" and an "adder". Such devices are costly in terms of required die area on an integrated circuit. It is desirable, therefore, to have an alternative method and apparatus for performing the translation, but one which dispenses with the multiplier/adder requirement.